1. Field of the Invention
The present invention relates to memory devices. In particular, the present invention relates to a memory device typified by a thin-film magnetic memory device including memory cells having an electrical resistance value varying according to the data level of storage data.
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device is now the focus of attention as a memory device capable of storing data in nonvolatile manner with low power consumption. The MRAM device uses a plurality of thin-film magnetic elements formed in a semiconductor integrated circuit to store data in nonvolatile manner, with each of the thin-film magnetic elements being used as a memory cell which is randomly accessible.
In recent years, it has been published that memory cells of thin-film magnetic elements with magnetic tunnel junctions are used to achieve dramatic improvements in performance of the MRAM device. The MRAM device including memory cells with magnetic tunnel junctions is disclosed for example in technical papers: xe2x80x9cA 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell,xe2x80x9d ISSCC Digest of Technical Papers, TA7.2, February 2000, xe2x80x9cNonvolatile RAM based on Magnetic Tunnel Junction Elements,xe2x80x9d ISSCC Digest of Technical Papers, TA7.3, February 2000 and xe2x80x9cA 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM,xe2x80x9d ISSCC Digest of Technical Papers, TA7.6, February 2001.
FIG. 16 schematically shows a structure of a memory cell having a magnetic tunnel junction (this memory cell is hereinafter referred to as xe2x80x9cMTJ memory cellxe2x80x9d).
Referring to FIG. 16, the MTJ memory (X greater than ) cell includes a tunneling magneto-resistance element TMR having an electrical resistance value varying according to the data level of magnetically written storage data and includes an access transistor ATR. The access transistor ATR is connected in series with the tunneling magneto-resistance element TMR between a bit line BL and a source line SL. The access transistor ATR is typically a field-effect transistor formed on a semiconductor substrate.
To the MTJ memory cell, the bit line BL and a digit line DL for allowing respective data write currents to flow in different directions respectively in data writing, a word line WL for conducting data reading, and the source line SL for pulling down the tunneling magneto-resistance element TMR to a fixed voltage (e.g. ground voltage GND) in data reading are provided. In data reading, the access transistor ATR is turned on and, in response to this turn-on, the tunneling magneto-resistance element TMR is electrically coupled between the source line SL and the bit line BL.
FIG. 17 conceptually shows an operation of writing data into the MTJ memory cell.
Referring to FIG. 17, the tunneling magneto-resistance element TMR includes a ferromagnetic layer FL having a fixed direction of magnetization (hereinafter referred to as xe2x80x9cfixed magnetic layerxe2x80x9d), and a ferromagnetic layer VL magnetized in a direction according to an externally applied magnetic field (hereinafter referred to xe2x80x9cfree magnetic layerxe2x80x9d). Between the fixed magnetic layer FL and the free magnetic layer VL, a tunneling barrier (tunneling film) TB formed of an insulating film is provided. According to the level of storage data to be written, the free magnetic layer VL is magnetized in the same direction as or in a different direction from the direction in which the fixed magnetic layer FL is magnetized. These fixed magnetic layer FL, tunnel barrier TB and free magnetic layer VL form a magnetic tunnel junction.
The tunneling magneto-resistance element TMR has an electrical resistance value varying according to a relative relation between respective directions of magnetization of the fixed magnetic layer FL and the free magnetic layer VL. Specifically, the tunneling magneto-resistance element TMR has a minimum electrical resistance value Rmin when the fixed magnetic layer FL has a magnetization direction which is the same as (in parallel with) that of the free magnetic layer VL and has a maximum electrical resistance value Rmax when respective magnetization directions of the fixed magnetic layer FL and the free magnetic layer VL are opposite to (in antiparallel with) each other.
In data writing, the word line WL is inactivated to turn off the access transistor ATR. In this state, a data write current for magnetizing the free magnetic layer VL flows through each of the bit line BL and the digit line DL according to the level of data to be written.
FIG. 18 conceptually shows a relation between the data write current and the magnetization direction of the tunneling magneto-resistance element in data writing.
Referring to FIG. 18, the horizontal axis H (EA) represents a magnetic field applied in the direction of an axis of easy magnetization (EA: Easy Axis) in the free magnetic layer VL in the tunneling magneto-resistance element TMR. The vertical axis H (HA) represents a magnetic field acting in the direction of an axis of hard magnetization (HA: Hard Axis) in the free magnetic layer VL. The magnetic field H (EA) and the magnetic field H (HA) correspond respectively to two magnetic fields generated by respective currents flowing through the bit line BL and the digit line DL.
In the MTJ memory cell, the fixed magnetization direction of the fixed magnetic layer FL is in parallel with the easy axis of the free magnetic layer VL, and the free magnetic layer VL is magnetized in the direction which is in parallel or antiparallel with (opposite to) the fixed magnetic layer FL in the direction of the easy axis. The MTJ memory cell is capable of storing 1-bit data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) according to the two magnetization directions of the free magnetic layer VL.
The magnetization direction of the free magnetic layer VL is only rewritable when the sum of the applied magnetic fields H (EA) and H (HA) falls within the region outside the asteroid characteristic line shown in FIG. 18. In other words, if the intensity of the applied data write fields corresponds to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL is not changed.
As indicated by the asteroid characteristic line, a magnetic field in the direction of the hard axis can be applied to the free magnetic layer VL to reduce a magnetization threshold which is necessary for changing the magnetization direction along the easy axis.
Suppose that operating points for data writing are designed as shown in FIG. 18. Then, for the MTJ memory cell into which data is to be written, a data write magnetic field in the direction of the easy axis is designed to have its intensity equal to HWR. More specifically, the value of a data write current flowing through the bit line BL or the digit line DL is designed to obtain this data write magnetic field HWR. In general, the data write magnetic field HWR is represented by the sum of a switching magnetic field HSW necessary for changing the magnetization direction and a margin xcex94H: HWR=HSW+xcex94H.
In order to rewrite storage data of the MTJ memory cell, i.e., rewrite the magnetization direction of the tunneling magneto-resistance element TMR, a data write current of at least a predetermined level must be flown through both of the digit line DL and the bit line BL. Accordingly, the free magnetic layer VL in the tunneling magneto-resistance element TMR is magnetized in the direction in parallel with or opposite to (antiparallel with) the fixed magnetic layer FL according to the direction of a data write magnetic field along the easy axis (EA). The magnetization direction once written into the tunneling magneto-resistance element TMR, i.e., storage data in the MTJ memory cell, is held in nonvolatile manner until execution of writing of new data.
FIG. 19 conceptually shows an operation of reading data from the MTJ memory cell.
Referring to FIG. 19, in the data reading operation, the access transistor ATR is turned on in response to activation of the word line WL. Then, the tunneling magneto-resistance element TMR pulled down to a predetermined voltage Vss is electrically coupled to the bit line BL.
In this state, the bit line BL is pulled up to a predetermined voltage to allow a memory cell current to flow through a current path including the bit line BL and the tunneling magneto-resistance element TMR Icell, according to an electrical resistance of the tunneling magneto-resistance element TMR, i.e., the level of storage data in the MTJ memory cell. For example, the memory cell current Icell can be compared with a predetermined reference current Iref (not shown) to read the storage data from the MTJ memory cell.
The tunneling magneto-resistance element TMR thus has its electrical resistance varying according to the magnetization direction which is rewritable by an applied data write magnetic field. Then, nonvolatile data storage can be executed by correlating electrical resistances Rmax and Rmin of the tunneling magneto-resistance element TMR respectively with levels (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d) of storage data.
As discussed above, for the MRAM device, data is stored by using a difference in electrical resistance that is a difference in junction resistance of the tunneling magneto-resistance element TMR according to a difference in level of storage data, i.e., xcex94R=(Rmaxxe2x88x92Rmin). In other words, a memory cell current flowing through a selected memory cell is sensed to read data.
For data reading, a reference cell is provided separately from a normal memory cell for storing data therein, the reference cell being used for generating the reference current to be compared with the memory cell current as described above. Such a reference cell is designed to have a value intermediate between two electrical resistances Rmax and Rmin of the MTJ memory cell.
In data reading, a current path for the memory cell current including a selected memory cell (hereinafter referred to as xe2x80x9cmemory cell current pathxe2x80x9d) and a current path for the reference current including a reference cell (hereinafter referred to as xe2x80x9creference current pathxe2x80x9d) are provided. Currents passed through respective paths are compared with each other to read data.
Generally, the tunneling magneto-resistance element has an electrical resistance of the level corresponding to a few tens of Kxcexa9. In data reading, a low voltage of approximately 0.5 V is applied to both of the two ends of the tunneling magneto-resistance element and accordingly a memory cell current of approximately 20 xcexcA is generated. In this case, a difference in current caused by the electrical resistance difference xcex94R discussed above is a few tens of xcexcA. Therefore, for sensing a difference in electrical resistance between the selected memory cell and the reference cell, the currents must be compared with a high sensitivity.
Then, if respective electrical resistances of those two current paths except for the selected memory cell and the reference cell (hereinafter referred to as xe2x80x9cpath resistancexe2x80x9d) are different to a great degree, the electrical resistance difference between the selected memory cell and the reference cell cannot be read precisely, resulting in deterioration in data reading precision.
MTJ memory cells of the MRAM device are generally arranged in rows and columns in integrated manner. Therefore, depending on the position of a selected memory cell indicated by address selection, at least the memory cell current path varies. Here, consideration must be taken not to change the difference in path resistance between the memory cell current path and the reference current path depending on the address selection. It is noted that such a problem is common to MRAM devices and memory devices including memory cells having an electrical resistance varying according to the level of storage data.
One object of the present invention is to improve a data reading margin of a memory device which reads data according to a difference in electrical resistance between a reference cell and a selected memory cell.
According to one aspect of the present invention, a memory device includes a memory array having a plurality of memory cells and a plurality of reference cells arranged in rows and columns, the plurality of memory cells each having one of electrical resistances of respective two levels according to storage data and the reference cells each being provided as a comparison target for selected one of the plurality of memory cells in data reading. The reference cells are arranged along one of the rows and the columns to share the other of the rows and the columns with the memory cells. The memory device further includes a plurality of word lines provided correspondingly to the rows respectively and activated in a selected row, a plurality of data lines provided correspondingly to the columns respectively, and a plurality of source lines provided correspondingly to that one of the rows and the columns respectively, the source lines each supplying a fixed voltage. The memory cells each include a storage element having an electrical resistance varying according to the storage data and an access element turned on in response to activation of corresponding one of the word lines, and the storage element and the access element are connected in series between corresponding one of the data lines and corresponding one of the source lines. The data lines include a first data line connected to a selected memory cell among the memory cells that is selected as a cell with data to be read in the data reading, and a second data line connected to a selected reference cell among the reference cells in the data reading, and the selected reference cell shares the other of the rows and the columns with the selected memory cell. The memory device further includes a data reading circuit coupling, in the data reading, the first and second data lines to a voltage different from the fixed voltage to form first and second current paths respectively passing the selected memory cell and the selected reference cell, and the data reading circuit reads the storage data from the selected memory cell according to a difference in electrical resistance between the first and second current paths.
One chief advantage of the present invention is that the first current path including the selected memory cell and the second current path including the selected reference cell are balanced, in terms of the length of the path on the source lines having a relatively high electrical resistance, regardless of the result of address selection, by providing reference cells in the direction which is the same as the direction in which the source lines are provided to extend. Accordingly, a difference in the total electrical resistance between the first and second current paths indicates a difference in electrical resistance between the selected memory cell and the selected reference cell, and thus the deterioration in data reading margin depending on the result of address selection is prevented to stabilize data reading operation.
According to another aspect of the present invention, a memory device includes a memory array having a plurality of memory cells and a plurality of reference cells arranged in rows and columns, the memory cells each having one of electrical resistances of respective two levels according to storage data and the reference cells each being provided as a comparison target for selected one of the plurality of memory cells in data reading. The reference cells are arranged along the rows to share the columns with the memory cells. The memory device further includes a plurality of word lines provided correspondingly to the rows respectively and activated in a selected row, a plurality of data lines provided correspondingly to the columns respectively, and a plurality of source lines provided correspondingly to the columns respectively, the source lines each supplying a fixed voltage. The memory cells each include a storage element having an electrical resistance varying according to the storage data and an access element turned on in response to activation of corresponding one of the word lines. The storage element and the access element are connected in series between corresponding one of the data lines and corresponding one of the source lines. The data lines include a first data line connected to a selected memory cell among the memory cells that is selected as a cell with data to be read in the data reading, and a second data line connected to a selected reference cell among the reference cells in the data reading. The selected reference cell shares the columns with the selected memory cell. The memory device further includes a data reading circuit coupling, in the data reading, the first and second data lines to a voltage different from the fixed voltage to form first and second current paths respectively passing the selected memory cell and the selected reference cell. The data reading circuit reads the storage data from the selected memory cell according to a difference in electrical resistance between the first and second current paths. An electrical resistance per unit length of the data lines is designed to be substantially equal to an electrical resistance per unit length of the source lines.
The above-discussed memory device has a configuration where reference cells are arranged along the row direction, and the source lines and data lines arranged in the column direction have respective electrical resistances per unit length that are substantially equal to each other. Then, regarding the first current path including the selected memory cell and the second current path including the selected reference cell, the electrical resistance of the first current path except for the selected memory cell is balanced with the electrical resistance of the second current path except for the selected reference cell, regardless of the result of address selection. Accordingly, a difference in the total electrical resistance between the first and second current paths indicates a difference in electrical resistance between the selected memory cell and the selected reference cell, and thus the deterioration in data reading margin depending on the result of address selection is prevented to stabilize data reading operation.
According to still another aspect of the present invention, a memory device includes a memory array having a plurality of memory cells and a plurality of reference cells arranged in rows and columns. The memory cells each have one of electrical resistances of respective two levels according to storage data. The reference cells are each provided as a comparison target for selected one of the plurality of memory cells in data reading. The reference cells are arranged along the columns to share the rows with the memory cells. The memory device further includes a plurality of word lines provided correspondingly to the rows respectively and activated in a selected row, a plurality of data lines provided correspondingly to the columns respectively, and a plurality of source lines provided correspondingly to the rows respectively, the source lines each supplying a fixed voltage. The memory cells each include a storage element having an electrical resistance varying according to the storage data and an access element turned on in response to activation of corresponding one of the word lines, the storage element and the access element being connected in series between corresponding one of the data lines and corresponding one of the source lines. The data lines include a first data line connected to a selected memory cell among the memory cells that is selected as a cell with data to be read in the data reading, and a second data line connected to a selected reference cell among the reference cells in the data reading, the selected reference cell sharing the rows with the selected memory cell. The memory device further includes first and second data buses provided along the rows in a region adjacent to the memory array, the first and second data buses being connected electrically to the first and second data lines in the data reading. The data reading circuit couples, in the data reading, the first and second data buses to a voltage different from the fixed voltage to form first and second current paths respectively passing the selected memory cell and the selected reference cell. The data reading circuit reads the storage data from the selected memory cell according to a difference in electrical resistance between the first and second current paths. An electrical resistance per unit length of the source lines is designed to be substantially equal to an electrical resistance per unit length of the first and second data lines.
The above-described memory device has a configuration with reference cells arranged in the direction of columns. The source lines and the first and second data buses arranged in the row direction are designed to have respective electrical resistances per unit length that are substantially equal to each other. Then, regarding the first current path including the selected memory cell and the second current path including the selected reference cell, the electrical resistance of the first current path except for the selected memory cell is balanced with that of the second current path except for the selected reference cell, regardless of the result of address selection. Accordingly, a difference in the total electrical resistance between the first and second current paths indicates a difference in electrical resistance between the selected memory cell and the selected reference cell, and the deterioration in data reading margin depending on the result of address selection is thus prevented to stabilize data reading operation.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.